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How semiconductor physics creates a hard ceiling for transistor miniaturization

July 22, 2026 · 13 min

Juniper Vale & Mark Delaney

Moore's Law collapsed in two stages: Dennard scaling — which kept power density flat as transistors shrank — broke around 2005, then quantum tunneling set a hard physical limit below ~10 nm channel lengths. Chiplets and 3D stacking buy time but cannot replicate the 40-year cost-per-transistor curve that made computing cheaper every two years.

Moore's Law, first articulated by Gordon Moore in a 1965 Electronics magazine article, observes that the number of transistors on a dense integrated circuit doubles approximately every two years, producing exponential gains in computing power alongside falling cost per transistor. Moore later revised his initial estimate of annual doubling to roughly every two years in 1975.

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About this episode

Moore's Law turns sixty this decade, and almost everything people think they know about it is slightly wrong. It wasn't a law. It wasn't even a stable prediction — Gordon Moore revised his original doubling-every-year estimate to every two years in 1975, and the industry adopted the new number as a planning target. That self-fulfilling loop — prediction becomes roadmap, roadmap becomes reality — is what this episode actually pulls apart. The deeper story is about two mechanisms that ran together for roughly four decades: transistor miniaturization and Dennard scaling, the insight from IBM that shrinking dimensions while proportionally reducing voltage kept power density flat. Faster, denser, and no hotter. That package deal ended around 2005, quietly, while marketing kept citing transistor counts as the headline number. Below about ten nanometers, the physics gets genuinely strange. Electrons tunnel through gates that are supposed to stop them, leaking current and generating heat that no cooling design can fully address. The episode walks through what that means structurally — and why proposed fixes like phosphorene nanoribbon transistors, though real and researched, haven't cleared the manufacturing hurdle. The back half lands on what actually happened next: chiplets, 3D stacking, AMD's approach to disaggregating dies. These work. But they don't reproduce the cost curve that made computation cheaper for a generation of developers and cloud users. Both the physics and the economics hit their limits around the same time. That coincidence is reshaping who can afford to build what — and it's happening without much fanfare.

Frequently asked

Why did Moore's Law stop working?

Moore's Law effectively broke in two steps. Around 2005, Dennard scaling collapsed — transistors kept shrinking but voltage could not follow, so power density rose instead of staying flat. Below roughly 10 nm, quantum tunneling allows electrons to leak through gate barriers, making classical silicon transistors physically unreliable regardless of manufacturing precision.

What is Dennard scaling and why does it matter for chip performance?

Dennard scaling, described by IBM's Robert Dennard in 1974, states that shrinking transistor dimensions while proportionally reducing voltage and current keeps power density constant. This let chips become simultaneously faster, denser, and no hotter for roughly four decades. When voltage stopped scaling around 2005, that free trade-off between speed, density, and efficiency ended.

What is quantum tunneling and how does it limit transistor size?

Quantum tunneling allows electrons to pass through a physical barrier rather than being blocked by it. In transistors below about 10 nm channel length, electrons tunnel through the gate instead of being switched off, causing leakage current. This leakage wastes power as heat and cannot be eliminated through better classical silicon design — it is a consequence of quantum mechanics.

Do chiplets and 3D stacking replace Moore's Law?

Chiplets and 3D stacking improve chip performance but do not replicate Moore's Law economics. Classical scaling simultaneously reduced cost, increased density, and improved energy efficiency from one engineering effort. Chiplets require separate costs for advanced packaging, power delivery, and bonding processes, so the cost-per-transistor curve no longer falls at the historical rate.

What are phosphorene nanoribbon MOSFETs and can they replace silicon?

Phosphorene nanoribbon MOSFETs are transistors built from phosphorene, an atomically thin 2D material. Electrons in phosphorene have anisotropic effective mass — appearing heavier in certain directions — which suppresses quantum tunneling leakage even at 1 nm channel lengths. The physics is promising, but consistent large-scale manufacturing of phosphorene has not been achieved as of current research.

Grounded in 12 sources
The 2D Materials Roadmap · arxiv.org
Saving Moore’s Law Down To 1 nm Channels With Anisotropic Effective Mass · doi.org
From Material Properties to System Architecture: Exploring Collaborative Pathways for Semiconductor Innovation in the Post-Moore Era · doi.org
Today’s computing challenges: opportunities for computer hardware design · pmc.ncbi.nlm.nih.gov
Dennard Scaling - an overview · sciencedirect.com
Moore’s Law@50: “The most important graph in human history” - CHM · computerhistory.org
Cramming More Components Onto Integrated Circuits - Proceedings of the IEEE · cs.utexas.edu
Chiplets past, present, and future: how advanced packaging is shaping silicon - Electrical Engineering News and Products · eeworldonline.com
Moore's law · en.wikipedia.org
Establishing Moore's Law · gwern.net
Advanced Semiconductor Packaging 2027-2037: Forecasts, Technologies, Applications: IDTechEx · idtechex.com
Is Moore's law dead? · imec-int.com
Read transcript

Mark Delaney: Juniper, long week — but I kept coming back to this one thing and I think it's gonna make for a genuinely weird episode.

Juniper Vale: Weird how?

Mark Delaney: Weird in that — okay, the thing we're talking about today, Moore's Law, everyone's heard of it, right? But it's not actually a law. It's a prediction one guy made in a magazine article in 1965. And then somehow sixty years of chip design just... followed it.

Juniper Vale: Gordon Moore, 'Cramming More Components onto Integrated Circuits,' Electronics Magazine. And the original prediction was doubling every year — he pulled it back to every two years in 1975.

Mark Delaney: Right, and — wait, he changed his own prediction and it still stuck? That's the part I don't understand.

Juniper Vale: It stuck because the industry grabbed the revised number and turned it into a target. Moore's Law is not a discovery about physics — it's a story about what happens when a prediction is made by someone with enough credibility and institutional weight that the whole industry decides to engineer around it.

Mark Delaney: And the credibility piece matters — I mean, Moore wasn't just some guy. He co-founded Intel with Robert Noyce in 1968. So the person making the prediction is also running one of the companies most responsible for hitting it.

Juniper Vale: You know, that's the part people skip. Intel was simultaneously the steward of the prediction and its primary engine. And Moore had come out of Fairchild Semiconductor, where this whole culture of competitive transistor scaling had already taken root. So the prediction didn't land in a vacuum.

Mark Delaney: It's like — uh, it's like someone with a really good batting average predicting they'll hit .300 next season, and then the whole league restructures its pitching to meet that number.

Juniper Vale: That's actually a decent analogy. The targets get set, people invest to meet them, the meeting validates the target. That's the self-fulfilling prophecy dynamic — observation becomes roadmap, roadmap becomes reality.

Mark Delaney: So what we're actually trying to figure out today is whether that loop can keep running — or whether there's a wall it finally hit.

Juniper Vale: And here's what the loop was actually running on — because that's the part that doesn't get explained. Think of a highway where every time engineers add more lanes, every car on it gets lighter, and the total fuel bill stays flat. That's what you had for thirty-odd years. More cars, same gas station.

Mark Delaney: Wait — the total bill stays flat even though there's more traffic?

Juniper Vale: That's the core of it. Feature-size scaling shrank the transistors — smaller gate, narrower channel — so you fit more on the same piece of silicon. And Robert Dennard, at IBM, figured out in 1974 that if you shrink those dimensions and proportionally reduce voltage and current at the same time, power density stays roughly constant. Faster, denser — and your chip doesn't get any hotter.

Mark Delaney: So those two things — the shrinking and the Dennard scaling — they were happening together. Like, they were a package deal.

Juniper Vale: Exactly a package deal. And that package is why you got simultaneous improvements in density, speed, and energy efficiency for roughly four decades. You didn't have to trade one for another. That almost never happens in engineering.

Mark Delaney: Huh. So what broke it?

Juniper Vale: Around 2005, the voltage stopped following the transistors down. You can only shrink voltage so far — below a certain threshold, the chip just doesn't switch reliably. So transistor dimensions kept shrinking, but power density started climbing. The heat side of that package deal quietly fell apart.

Mark Delaney: Hold on. 2005 — that's twenty years ago. And I — uh, I don't remember anyone saying that out loud.

Juniper Vale: Nobody did. Transistor counts kept climbing, and the spec sheets kept advertising those counts. Intel, TSMC — everyone's marketing kept citing transistor density as the headline number. The efficiency gains had stopped, but the density story was still technically true, so that's the one that got told.

Mark Delaney: So if you bought a laptop in, I dunno, 2008 — it wasn't getting more power-efficient year over year even though the chip had more transistors on it.

Juniper Vale: No, it wasn't. The chip was running hotter, which is actually why you started seeing multi-core designs proliferate — you couldn't clock a single core faster without melting it, so the industry spread the work sideways. That was the workaround. Not a solution to the Dennard scaling collapse, a response to it.

Mark Delaney: So the free ride ended in 2005 and we just... kept buying tickets like it hadn't.

Juniper Vale: And the ticket is about to get a lot more expensive — because there's a layer underneath the Dennard story that's genuinely weirder. Picture a teenager, right now, rendering a game scene on a high-end GPU laptop. Fan screaming, chassis hot enough to leave a mark on her leg. That heat is not a bad cooling design. That is physics arriving at the surface.

Mark Delaney: The physics itself is — wait, what do you mean arriving at the surface?

Juniper Vale: Below about ten nanometers — channel lengths, the actual path electrons travel through the transistor — electrons stop behaving classically. They don't wait to be switched. They ghost through the gate. Quantum tunneling. The wall you built to control them just... isn't there for them.

Mark Delaney: Hold on. They pass through a wall that's physically there?

Juniper Vale: That's exactly what tunneling is, yeah. And the consequence is leakage current — electrons bleeding through when the transistor is supposed to be off. You lose gate control, you're burning power constantly, and that power becomes heat you cannot engineer away. It's not a design flaw. It's quantum mechanics.

Mark Delaney: So the teenager's laptop isn't hot because the cooling is cheap. It's hot because — uh, because the chip is basically leaking electricity through walls that are too thin to hold.

Juniper Vale: That's the right frame. And it's not solvable by being cleverer with classical silicon. The leakage grows as you shrink — it's structural, not a mistake.

Mark Delaney: Okay but — I mean, is this actually a hard wall? Or is it another one of those 'we said we couldn't do it and then we did' moments?

Juniper Vale: So there's research — and it's real, not vaporware — on channel materials where electrons have what's called anisotropic effective mass. Different apparent weight in different directions. The idea is you pick a direction where the electron is heavy enough that it can't tunnel easily, and that suppresses source-to-drain leakage even at one nanometer channels. Phosphorene nanoribbon MOSFETs are the studied example. But commercial yield — actually manufacturing these at scale — that part is completely unresolved.

Mark Delaney: Phosphorene — that's a 2D material? Like graphene?

Juniper Vale: Same family, yeah. Graphene, phosphorene, transition metal dichalcogenides — all atomically thin. All proposed as silicon replacements for sub-nanometer channels. All facing the same problem: nobody's cracked how to grow them consistently enough to put in a product. The physics is promising. The factory floor is a different conversation.

Mark Delaney: So the industry found a workaround for the Dennard collapse — went multi-core, went wider — and now there's a separate wall at the atomic level that a different set of workarounds is trying to climb. And the workarounds we haven't talked about yet — chiplets, 3D stacking, what AMD did — that's actually where the money moved, and why the economics got strange in a whole new way.

Juniper Vale: That's exactly where this goes next. And I'll say upfront: those approaches work. They're not fake. But they don't replicate what made classical scaling so absurdly cheap, and that difference is the whole ballgame.

Mark Delaney: Okay but — right, so AMD just... did it. Like, they didn't wait for the physics to cooperate, they just cut the chip into pieces.

Juniper Vale: That's the chiplet idea, yeah. Instead of one massive die with everything on it, you disaggregate — you break the functions apart into smaller separate dies, manufacture them independently, then assemble them into one package. AMD was doing versions of this by 2011, starting with a sliced FPGA approach. And the yield math alone makes it worth it.

Mark Delaney: Wait — yield? Like, how many chips don't explode during manufacturing?

Juniper Vale: Roughly, yes. A larger die has more surface area where a defect can kill the whole thing. Smaller dies fail less often, so you throw away less silicon. And the chiplet move lets you mix process nodes — you put the cutting-edge transistors only where you need them, run the less critical parts on an older, cheaper node. That's not consolation-prize engineering. That's real.

Mark Delaney: Huh. And the 3D stacking piece — that's different, or is that the same move?

Juniper Vale: Different mechanism. 3D stacking goes vertical — you connect chip layers through short vertical interconnects called through-silicon vias. AMD's VCache does this, stacks cache memory directly on top of the processor. You're getting effective density without shrinking any feature laterally. The interconnects are short enough that you don't pay the power penalty you'd pay routing signals across a board.

Mark Delaney: That's — okay, that's actually clever. So is this basically the new Moore's Law, then?

Juniper Vale: I mean — no. And this is the honest answer. These approaches work, but they don't replicate the economics. Classical scaling gave you density and efficiency and lower cost, all from one engineering effort. Chiplets and 3D stacking give you performance gains, but the cost-per-transistor curve doesn't follow the same slope. You're paying separately for packaging, power delivery, the advanced bonding process. It's not free anymore.

Mark Delaney: So — uh, wait. I'm trying to make this concrete. A game developer buying server time to run AI training — does she feel that cost difference?

Juniper Vale: She does. Because cloud computing and AI training were both built on the assumption that cheap computation would keep getting cheaper at the classical rate. The whole pricing model assumed that. When the cost-per-transistor economics stop delivering, the bill for that training run doesn't keep dropping the way it would have in 2005.

Mark Delaney: No kidding. And fabrication costs — I've heard those are just brutal now at the advanced nodes.

Juniper Vale: Yeah, and that's actually — this is the part that doesn't get said enough — classical scaling was also hitting a financial wall before the physics fully closed in. The per-transistor cost at the most advanced nodes has actually flattened or risen. So chiplets also exist because continued monolithic scaling is financially untenable, not just physically hard. It's solving two problems at once.

Mark Delaney: So the hidden subsidy — the one that made everything cheaper for forty years — it ended for money reasons AND physics reasons at basically the same time.

Juniper Vale: Both bills came due together. That's the actual situation the industry is in. The workarounds are real, and they're buying time — but the model where consumers just passively inherit cheaper computation every two years? That model needed Gordon Moore's specific machine to keep running. And that machine has stopped.

Mark Delaney: The thing that actually landed for me — uh, and I'm still kind of chewing on it — is that Moore's Law was never a promise from physics. It was a promise the industry made to itself. And it kept that promise for forty years because two mechanisms were running together. Feature-size scaling and Dennard scaling. And when both of those quietly stopped, the promise just... didn't get renewed. Nobody sent the memo.

Juniper Vale: And the self-fulfilling prophecy dynamic cuts both ways. When it's running, it's a machine — predictions become targets, targets get met, that validates the prediction. But when the underlying mechanics break, the social machinery keeps going a little longer than it should. Gordon Moore made an observation. The industry turned it into an obligation. Those are not the same thing.

Mark Delaney: Which means AI training costs, cloud pricing — all of that was built on an assumption that was already quietly expiring.

Juniper Vale: Yeah. If chiplets and 3D stacking can't replicate the classical cost-per-transistor curve — and right now they can't — then some of those compute-heavy problems just get more expensive. Not unsolvable. Just not cheap the way everyone planned for.

Mark Delaney: And that reshapes who gets to build what.

Juniper Vale: Quietly, yeah. That's the honest shape of it.

Mark Delaney: I'm glad we actually said that out loud instead of just landing on 'chiplets are cool, we're fine.'

Juniper Vale: Chiplets are cool. We're not necessarily fine. Both things.

How semiconductor physics creates a hard ceiling for transistor miniaturization · Onpode