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How transistor shrinking works and where quantum tunneling becomes the wall

October 14, 2026 · 13 min

Iris Holm & Cyrus Reed

Transistor size shrinking diverged from Moore's Law's ideal curve as early as 1987, yet density kept climbing through coordinated industry investment. Below roughly 10 nanometers, quantum tunneling forces electrons through a nominally 'off' gate — a wall the field understood since the 1980s but is still racing to engineer around.

Moore's Law is an empirical observation — not a physical law — first articulated by Gordon Moore in 1965 while he was director of R&D at Fairchild Semiconductor. Moore observed that the number of components on an integrated circuit had been roughly doubling annually and projected continued growth. In 1975, after co-founding Intel, he revised the doubling cadence to approximately every two years.

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About this episode

For sixty years the semiconductor industry ran on a metronome: transistor count doubles roughly every two years, performance follows, and every fab, investor, and chip designer sets their clock to it. The episode traces how that metronome actually worked — and why it worked even when the underlying physics had already started to disagree. It starts with a fact that should reframe everything: transistor size scaling diverged from the ideal Moore's Law curve in 1987. Density kept climbing anyway. What filled the gap wasn't physics — it was coordinated capital. Intel, Samsung, ASML, and their suppliers all committed to the same schedule, which gave everyone a financial reason to make it land. The target became load-bearing infrastructure. Then the episode gets into what finally broke it: quantum tunneling. Below roughly ten nanometers, the gate oxide layer in a conventional MOSFET becomes so thin that electrons pass through it even when the transistor is switched off. The fix — thickening the insulator — just trades one leakage problem for another. The geometry runs out of room. Three-dimensional architectures like FinFETs and GAAFETs delay the problem by wrapping more gate surface around the channel. 3D chip stacking sidesteps shrinking entirely by packing more dies into vertical space. Both are real — but they carry different failure modes and a much shorter prediction horizon than planar scaling ever offered. The industry isn't lost. It's just navigating without the instrument it relied on for half a century.

Frequently asked

How does transistor shrinking work?

Transistor shrinking works by reducing the gate length of a MOSFET so it switches faster and more transistors fit per unit area. For decades the playbook was straightforward: smaller gate, faster switching, higher density. Physical gate-length scaling, however, stopped matching the ideal Moore's Law curve around 1987, even as density kept rising.

What is quantum tunneling in transistors and why does it matter?

Quantum tunneling in transistors occurs when the gate insulating layer shrinks below roughly 10 nanometers and electrons pass through it even when the transistor is switched off. This creates leakage current that cannot be eliminated by design. Multiplied across billions of transistors, the effect causes power dissipation that stopped clock-speed growth around 2004–2005.

When did Moore's Law effectively end?

MIT computer scientist Charles Leiserson places Moore's Law's end around 2016, citing Intel's delay from its 14 nm node to 10 nm — a transition that took five years instead of the two-year cadence Moore's Law prescribed. Gordon Moore himself revised his original 1965 annual-doubling prediction to every two years as early as 1975.

Do FinFETs and GAAFETs solve the quantum tunneling problem?

FinFETs and GAAFETs delay quantum tunneling rather than solve it. By wrapping the gate around more surface area of the channel, both architectures improve electrostatic control and reduce leakage — buying additional process nodes. The channel is still silicon, however, so the same carrier-mobility and tunneling limits ultimately remain in effect.

Can 3D chip stacking replace transistor shrinking?

3D chip stacking increases compute density by connecting multiple chips vertically rather than shrinking planar transistors further. ASML argues this continues Moore's Law; Charles Leiserson calls it a category error. Stacking introduces its own physical limits — thermal buildup, power delivery through vertical interconnects — whose ceilings are not yet fully mapped.

Grounded in 12 sources
Research on Innovation Path of 3D Transistor Architecture ↗ · doi.org
Beyond Moore's Law: a Simulation Driven Study of VLSI Scaling, AI Assisted Design Automation, and Emerging Technologies ↗ · doi.org
Gate structuring on n-type bilayer MoS2 field-effect transistors for ultrahigh current density. ↗ · doi.org
Quantum Mechanical Simulations of Current Flow in Carbon Nanotubes Transistors ↗ · doi.org
Multigate transistors: Pushing Moore's law to the limit ↗ · doi.org
A new line tunneling SiGe/Si iTFET with control gate for ... - PMC ↗ · pmc.ncbi.nlm.nih.gov
Leakage currents | IEEE Technology Navigator ↗ · technav.ieee.org
Gate leakage | IEEE Technology Navigator ↗ · technav.ieee.org
Quantum Effects in Microelectronics ↗ · medium.com
The ongoing evolution of Moore’s Law – Stories | ASML ↗ · asml.com
Moore's Law Explained: Past, Present, and What Comes Next ↗ · datacamp.com
Moore's Law - Electronics Reference ↗ · electronicsreference.com
Read transcript

Cyrus Reed: Iris, hey — I have to ask, did you go into this one already convinced it was going to make me uncomfortable?

Iris Holm: I didn't have to try. The material does it on its own. Here — I want to hand you a sentence and have you sit with it. Moore's Law is not a law.

Cyrus Reed: Yeah, okay, I've heard that — it's an observation, not a physical law, sure.

Iris Holm: No, go further. Gordon Moore publishes it in 1965 — he's at Fairchild Semiconductor, director of R&D — he sees transistor count doubling annually and projects it forward. Then in 1975, after co-founding Intel, he revises it to every two years. He changed his own observation. That's not a law. That's not even a stable prediction.

Cyrus Reed: Wait, he revised it himself — so the entire fifty-year story runs off a number that its own author walked back?

Iris Holm: And the industry didn't blink. It took the revised cadence and built roadmaps around it. Quarterly targets, fab investment cycles, everything.

Cyrus Reed: So then David House takes Moore's two-year doubling and translates it — chip performance doubles every eighteen months, no additional power draw. That's the version that actually becomes the cultural contract, right? Not transistor count, not gate length — performance per watt on an eighteen-month clock.

Iris Holm: Frankly, that's the version that matters most and gets cited least. House was also at Intel. The company was, in effect, narrating the target it was trying to hit.

Cyrus Reed: Which is — I mean, that's a little circular, isn't it? The company co-founded by Moore is also the company defining what his law means in practice.

Iris Holm: Now here's the number that should bother you more than any of that. Transistor size scaling — the actual physical shrinking — stopped matching the ideal Moore's Law curve in 1987. Not recently. 1987. And density still tracked it for decades after.

Cyrus Reed: No way — 1987 is almost the beginning of the story everyone tells. How is the size stopping then but density still climbing?

Iris Holm: That's the gap. The prediction and the outcome diverged, and the outcome kept going anyway. Something other than physics was doing the work.

Cyrus Reed: Something other than physics — okay, that's the thing I want to pull on, because here's the intuition I keep landing on. Imagine you and a group of friends all agree publicly that you're going to run a mile every ten minutes. And because everyone committed, because the whole group is watching, you actually do it. Not because your legs got faster. Because the social pressure made it true. That's what the semiconductor industry did with Moore's Law for forty years.

Iris Holm: Coordination dressed up as physics.

Cyrus Reed: Exactly — wait, no, I want to be more specific than that. It's not just coordination. It's coordination with money behind it. Intel commits capital to a node, Samsung commits capital to a node, equipment suppliers like ASML commit to the tooling — and now everyone has a financial reason to make the schedule land. The target becomes load-bearing infrastructure.

Iris Holm: Right. And then the infrastructure fails. 14nm to 10nm — five years. 2014 to 2019.

Cyrus Reed: Five years for one node. On a two-year cadence.

Iris Holm: And that's the moment Charles Leiserson at MIT points to. He doesn't say Moore's Law wobbled. He says it ended — around 2016 — and the Intel delay is his evidence.

Cyrus Reed: But wait — so what broke? Was it the coordination that broke, or was it actually physics stepping in and saying no, we're done here?

Iris Holm: That's the question. And I don't think it's clean. Physics was always the ceiling. Coordination was just — it was the mechanism getting you to the ceiling faster. When the ceiling arrived, coordination couldn't substitute.

Cyrus Reed: Which means — okay, so picture a chip designer at Intel in 2015, actually sitting down to plan a product roadmap. They write in: 10nm node arrives in 2016. That assumption is already baked into silicon orders, into hiring plans, into delivery promises to customers — before anyone has confirmed the physics can do it.

Iris Holm: And the node doesn't arrive until 2019. So three years of commitments are sitting on a schedule that physics broke.

Cyrus Reed: That's — huh. So the social contract doesn't just collapse quietly. It's already embedded in contracts, in customers' products, in hiring. When it slips, the damage is everywhere at once.

Iris Holm: Which is why ASML doesn't say the law ended. If the law ended, a lot of promises are retroactively broken. The question is whether the industry can find a new mechanism to make the same kind of promises — or whether it has to stop making them.

Cyrus Reed: And that gap — between 'the physics should stop us' and 'when it actually did' — that's the part I keep wanting to understand mechanically. Like, what is the actual physics that finally said no?

Iris Holm: The MOSFET. That's where it lives. For decades the playbook was just — make the gate smaller, the transistor switches faster, pack more in. Simple.

Cyrus Reed: Right, the Metal-Oxide-Semiconductor Field-Effect Transistor — the gate sits on top of an insulating layer and controls whether current flows through the channel underneath.

Iris Holm: And the insulating layer is the problem. Below roughly ten nanometers, it gets so thin that electrons don't wait to be switched on. They tunnel through.

Cyrus Reed: Quantum tunneling — wait, so the transistor is nominally off and current is still flowing? That's not a bad transistor, that's — I mean, that's the transistor doing quantum mechanics at you.

Iris Holm: Correct. And the obvious fix — thicken the insulator back up — doesn't work.

Cyrus Reed: Why not, though? Like — okay, I'm genuinely asking, not being contrarian — if the layer is too thin, just make it thicker?

Iris Holm: Thicker insulator means the gate loses control of the channel. Short-channel effects take over — threshold voltage goes variable, leakage goes up anyway through the channel itself. You've traded one physics problem for the same physics problem wearing a different hat.

Cyrus Reed: So it's actually — wait, no, that's a trap with no exit. You can't thin the insulator, can't thicken it. The geometry just runs out.

Iris Holm: And multiply that leakage current across a chip with billions of transistors. Every transistor that's nominally off is still dissipating power. That's the power dissipation wall. It's why clock speeds stopped climbing in the mid-2000s — not because processors ran out of transistors, because they ran out of ways to shed heat.

Cyrus Reed: That's the part I didn't have properly connected. The speed plateau in like 2004, 2005 — that's not a design choice, that's leakage current making the chip a space heater.

Iris Holm: And we knew. This is the part that should be uncomfortable. Quantum tunneling through gate dielectrics — the physics has been understood since the 1980s. This is not a surprise the industry absorbed. It's a wall they saw from twenty years out.

Cyrus Reed: Which means — okay, so FinFETs, GAAFETs, all the three-dimensional transistor architectures — those aren't emergency pivots, are they? They're the contingency plan that took two decades to actually execute. And I want to get into whether that's real progress or just a very expensive way of relabeling the problem.

Iris Holm: That's the next question. Whether the architecture buys real headroom or just redefines what 'scaling' means so the roadmap can keep running.

Cyrus Reed: But wrapping the gate around a fin-shaped channel, surrounding it completely with a GAAFET, stacking n-type and p-type vertically in a CFET — all of that is improving electrostatic control without making the gate any smaller. So is that actually progress on the original problem, or is it — wait, no, I think that's the wrong frame. The original problem was leakage. And these fix leakage?

Iris Holm: They delay it. The gate wraps more surface area around the channel — more control, less leakage. But the channel is still silicon. The same carrier mobility limits still apply.

Cyrus Reed: So FinFETs bought us nodes. GAAFETs buy us more nodes. But they're buying time, not solving the underlying thing.

Iris Holm: And then you go to 3D chip stacking — heterogeneous integration, chiplets connected vertically with dense interconnects — and now you've left the transistor entirely. You're not shrinking anymore. You're just packing more chips into a smaller volume.

Cyrus Reed: Which is the move ASML defends, right? They say Moore's Law continues because density per unit area is still improving — just via stacking now instead of shrinking.

Iris Holm: And Charles Leiserson calls that a category error. Moore's Law described planar gate shrinking. Calling 3D stacking by the same name doesn't make it the same process.

Cyrus Reed: But — okay, how do you adjudicate that? Like, if the outcome is more compute per unit area over time, does the mechanism actually matter for the roadmap?

Iris Holm: It matters for what you can promise. Planar shrinking had predictable physics — a geometry you could model. Stacking has thermal limits, power delivery problems, interconnect density ceilings. Different failure modes, different prediction horizon.

Cyrus Reed: Huh — so the confidence interval on the roadmap just quietly blew out, and nobody issued a press release.

Iris Holm: Samsung's racing the same architecture bets Intel is. Neither has announced the problem solved. They've announced the problem relocated.

Cyrus Reed: Okay but what about the actually speculative stuff — MoS2, carbon nanotube transistors. Because those aren't moving the deck chairs, right? A single-atomic-layer material that retains semiconducting properties, or carbon nanotubes with quantum mechanical transport — those are genuinely different physical regimes.

Iris Holm: Frankly? Whether MoS2 actually outperforms silicon in practice remains questionable. That's not my hedge — that's the field's hedge. No material has shown production-scale viability. We're still measuring against simulations and early experiments.

Cyrus Reed: So we've got — wait, let me actually say this out loud because I want to see if it lands — we've got 3D architectures that are real but redefine the metric, and 2D materials that keep the metric but aren't manufacturable yet. Both of them are keeping a dead prediction alive by different means.

Iris Holm: Moore's Law's replacement wearing its clothes. That's the question the roadmap won't answer for you.

Cyrus Reed: And that's the part I actually can't shake loose. For sixty years there was a metronome — two-year cadence, every fab, every investor, every designer setting their clock to it. And now that metronome is just... absent. What do you even build a roadmap on when the shared beat is gone?

Iris Holm: That's where I keep sitting. It's not that the industry is lost. 3D stacking is real. Heterogeneous integration is real. But none of those are a law. They're a collection of bets, each with their own unknown failure mode.

Cyrus Reed: Right — but the part that doesn't fit for me is, okay, we went vertical specifically because we hit the physics wall going flat. But stacking has physics too. Thermal buildup in the layers, power delivery through vertical interconnects, heat that's got nowhere to go because you've sandwiched it inside the stack. That's not a solved problem. We don't even know yet where that wall is.

Iris Holm: We don't. And that's the honest answer nobody wants to say out loud. The semiconductor industry isn't navigating blind — but it's navigating without the instrument it used for half a century. That's a genuinely different situation.

Cyrus Reed: I mean — I came in thinking this was a story about physics catching up with prediction. But it's actually a story about what happens after the infrastructure holding everything together quietly stops working. And I don't think I have a clean answer to that.

Iris Holm: Neither do I. And I think that's the correct place to stop.