Eliza Ward: I have a question before we get into any of this — do you think you're getting more computing power for your money than you were five years ago?
Brian Reed: Honestly? I assumed yes, but I realize I have no actual basis for that. It just feels true.
Eliza Ward: That instinct comes from fifty years of Gordon Moore being right. 1965 — he observed that transistor density doubles roughly every two years. It held. The industry built roadmaps around it, priced hardware against it, designed software assuming it.
Brian Reed: And now it doesn't hold.
Eliza Ward: Now — actually, since around 2010 measurably — it bends. Pat Gelsinger at Intel said it plainly in late 2023: the doubling cadence is closer to three years now, not two. But wait, that's not actually the sharpest part.
Brian Reed: What's the sharpest part?
Eliza Ward: Moore's original promise wasn't just density. It was density *and* falling cost per transistor. Those were bundled. And at the nodes TSMC is manufacturing now — 3 nm, approaching 2 nm — advanced nodes actually cost *more* per transistor than older ones did. The promise isn't just slower. It's running backward on the cost side.
Brian Reed: That's — okay, I did not have that. So the density is still — I mean, sort of — creeping forward, but the economics flipped.
Eliza Ward: And below about 5 nm you hit quantum tunneling — electrons pass through the transistor gate when they're supposed to be blocked. The switch leaks. Which is why the industry didn't keep pushing the same lever. They changed levers entirely.
Brian Reed: So the thing we're really trying to figure out here is — if shrinking transistors is no longer how you get better chips, what is?
Eliza Ward: And whether that change was a solution — or just a very expensive workaround that concentrates who actually benefits.
Brian Reed: But before we get to the workaround — I want to stay with the leak for a second, because I don't think I actually have it yet. The light switch image keeps coming back to me. You've got a transistor — it's supposed to be off — and it's still letting current through. Why can't someone just... fix the switch?
Eliza Ward: That's the thing. It's not a defect you can fix.
Brian Reed: Wait — not fixable at all?
Eliza Ward: Below roughly 5 nanometers, electrons don't behave like marbles you can block with a wall. Quantum mechanically, they have a probability of just... appearing on the other side. The barrier is there. The electron ignores it. That's quantum tunneling — it's not an engineering mistake, it's physics.
Brian Reed: So the gate oxide — the material that's supposed to act as the barrier — becomes, I mean, essentially transparent at that scale?
Eliza Ward: Probabilistically transparent, yeah. And once that leakage current flows, it does three things at once — wastes power, generates heat, and corrupts the charge that's supposed to encode a one or a zero. The chip genuinely can't tell on from off anymore.
Brian Reed: Okay and — hang on — the heat part compounds it? Like it's not two separate problems, they're feeding each other?
Eliza Ward: Right, that's the second wall. Pack more transistors into a smaller area — which is the whole point of shrinking — and your power density spikes. Cooling just can't keep up. There's a thermal wall that's actually independent of the tunneling problem, and they arrive together at these scales. TSMC running at 3 nm is living inside both of those constraints simultaneously.
Brian Reed: Let me try to make this concrete — imagine someone designing a chip for, I don't know, a surgical robot controller. They need more compute, they want to shrink the node, and below 5 nm they're not getting a faster chip, they're getting a chip that leaks, heats, and starts misreading its own signals. That's the actual failure mode?
Eliza Ward: That's exactly it. And there are names for the specific mechanisms — short-channel effects, drain-induced barrier lowering — but they all cash out the same way: transistor behavior degrades. The device stops being a reliable switch well before 20 nm gate lengths, actually.
Brian Reed: Sub-20 nm — so this isn't only a 3 nm problem. TSMC approaching 2 nm is just the sharpest edge of something that's been biting for a while.
Eliza Ward: Confirmed. Which is why — wait, this is the pivot — the industry didn't fix the physics. They decided not to need it. GPUs, Google's TPU, the whole move toward domain-specific chips — none of that solves quantum tunneling. It just routes around it.
Brian Reed: So the physics is real, it's hard, and the answer was... change the question entirely.
Eliza Ward: Yeah — change the question entirely. And that's exactly what a graduate student submitting a neural network training job at eleven at night is actually living inside, without knowing it. Her model doesn't run on a general-purpose processor. It runs on Google's TPU cluster.
Brian Reed: TPU — the Tensor Processing Unit. Google's custom chip.
Eliza Ward: Custom ASIC. Designed from scratch for one job — matrix multiplications. That's it. Not general computation, not running your browser, not balancing a spreadsheet. One thing, done at a speed and efficiency no shrunken CPU could touch.
Brian Reed: So she gets her result faster because Google built a chip that only does her specific math?
Eliza Ward: And the reason it's faster isn't transistor count. It's the architecture underneath — systolic arrays. Data flows rhythmically through a grid of simple processors. Each one does one operation and passes the result to its neighbor. The efficiency is baked into the structure, not the shrinkage.
Brian Reed: Hang on — is that actually different in kind from what NVIDIA's GPUs do? Because I keep wanting to say they're just... better CPUs.
Eliza Ward: Genuinely different. NVIDIA runs thousands of parallel threads — that's the architecture, parallelism optimized for graphics and AI workloads. Google's TPU runs systolic arrays tuned for tensor operations specifically. Neither is a shrunken CPU. They're not on the same axis.
Brian Reed: That's — okay, I think I had those two collapsed in my head. So domain-specific means the architecture itself is the performance lever, not the node size.
Eliza Ward: Right — and the pivot to that started around 2010, when Moore's original cadence started bending. This wasn't an accident. Someone decided — actually, a lot of someones decided — that architectural specialization was the better bet. Gordon Moore's observation guided fifty years of investment. These companies looked at TSMC's 3 nm wall and said, let's bet on structure instead.
Brian Reed: Which is — I mean, that's what makes it durable, right? It's not a stopgap. It's a deliberate strategic reorientation.
Eliza Ward: That's the claim. And the thing that makes me actually believe it is that the grad student's training job wouldn't exist at that speed without the TPU — not because transistors failed her, but because matrix multiplication is a narrow enough problem that you can build an architecture that's almost nothing else. The workload fit the chip by design.
Brian Reed: But that's — wait, that's also the trap, isn't it? Her workload fits. What about the workload that doesn't fit any of these? The part I keep not asking is who this actually benefits — and I think that's where the cost curve stuff becomes the real story.
Eliza Ward: That's exactly what we need to get into next — because the cost curve inverting at advanced nodes is a separate break, and who specialization actually serves — hyperscalers versus everyone else — that's not settled.
Brian Reed: The cost curve inverting — I keep almost letting that slide past me, and I shouldn't. Because that's not just 'Moore's Law slowing.' That's Moore's Law breaking on the dimension that made it matter to anyone who wasn't a physicist.
Eliza Ward: Name the original promise exactly: more transistors AND cheaper per transistor. Density and cost reduction, bundled. Those were inseparable for fifty years.
Brian Reed: And now they've decoupled.
Eliza Ward: Completely. At 3 nm — what TSMC is running now — you pay more per transistor than you did at 28 nm. The density crept forward, the cost went the wrong direction.
Brian Reed: Hold on. So a chip designer buying 28 nm capacity is actually getting a better deal per transistor than someone at the cutting edge?
Eliza Ward: On cost per transistor, yes. Intel, Samsung, TSMC are all still competing at advanced nodes — but the reason isn't 'transistors got cheaper again.' It's that the differentiation shifted to architecture, to domain specificity. They're not competing on the original metric anymore.
Brian Reed: Right — but the part that doesn't fit is, EUV lithography. I mean, that's a real thing — 13.5 nm wavelength light, enables 7 nm nodes and beyond. imec is analyzing whether that path actually extends the law or just... delays the reckoning by five years.
Eliza Ward: EUV keeps density moving. It does not restore the two-year cadence, and it absolutely does not restore the cost guarantee. Those are two different claims and they're getting collapsed into one.
Brian Reed: And 3D stacking — stacking circuit layers vertically instead of shrinking flat — that's gaining real momentum. I mean, the argument is you get density and performance without pushing gate lengths smaller. But wait, actually — doesn't the heat problem get worse? You're piling heat sources on top of each other.
Eliza Ward: That's the unresolved tension nobody's cleanly solved. 3D integration worsens heat dissipation. The thermal wall they were trying to escape gets taller when you stack. It's not a patch — it's a tradeoff that imec has flagged publicly as genuinely open.
Brian Reed: So picture a hospital buying a new imaging analysis server this quarter. The sales pitch is 'cutting-edge node, maximum performance.' They're paying the advanced-node premium — more per transistor than last generation — and the performance gain is real, but it's coming from architectural choices, not shrinkage. They don't know that. They think they're buying Moore's Law.
Eliza Ward: And if their workload fits a Google TPU or an NVIDIA GPU, the gain is real. If it doesn't — if it's some weird hybrid compute problem — they're paying the advanced-node price for general-purpose hardware that isn't improving the way Moore's original promise said it would.
Brian Reed: That's the split, isn't it. Google built the TPU, captures the efficiency. Everyone else is either renting Google's specialization or buying general-purpose silicon at a price that no longer comes with the cost-reduction guarantee baked in. That's a market structure story now — not a physics one.
Eliza Ward: Yeah, and that's the thing that actually clicked for me somewhere in the middle of all this — Moore's Law didn't fail. It got replaced. Deliberately. And the replacement system answers a different question.
Brian Reed: A different question meaning — not 'can we make transistors smaller' but 'does your workload have a chip yet.'
Eliza Ward: Exactly that. And the gap it leaves — the actual gap — is that transformer-based AI models, the architecture that's running half the interesting things happening right now, those arrived before dedicated hardware existed for them. They ran on general-purpose processors. Processors that weren't scaling anymore. That's not a hypothetical orphaned workload. That happened.
Brian Reed: So there was a window where — I mean, the workload existed, the compute need was real, and the hardware hadn't caught up yet because no one had decided it was worth building.
Eliza Ward: Right. And when shrinkage was the lever, that gap closed automatically — you just waited a node cycle and everything got faster for free. Now someone has to decide to build the chip. That's a market decision. Investment follows large, well-defined workloads. Novel or diffuse problems wait.
Brian Reed: That's — yeah. That's actually the part that settles it for me. It's not a physics constraint anymore, it's a capital allocation one. Which is a different kind of hard.
Eliza Ward: Different kind of power, too. Gordon Moore's observation was neutral — physics doesn't pick winners. This system does.
Brian Reed: That's where I'll sit with it. Thanks for pulling all that apart — the cost curve piece especially, I kept almost letting that go.
