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The physics wall: why transistor scaling hits diminishing returns below nanometer scales

October 7, 2026 · 14 min

Juniper Vale & Hope Sterling

Transistor scaling hits a hard physics wall below roughly three nanometers because electrons tunnel through insulating barriers as quantum waves, ignoring engineering workarounds. Meanwhile, high-NA EUV lithography scanners cost over $350 million per unit, making advanced nodes economically viable only for AI accelerators — not general-purpose chips.

Moore's Law originated with Gordon Moore's 1965 article in Electronics magazine, where Moore — then director of R&D at Fairchild Semiconductor — observed that the number of components on integrated circuits was doubling approximately annually. In 1975, Moore revised the doubling period to roughly every two years, which became the widely cited formulation.

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About this episode

Moore's Law is one of those ideas everyone invokes and almost nobody examines. It wasn't derived from physics — Gordon Moore just noticed a pattern in 1965, and that pattern held, roughly, for sixty years. This episode tries to figure out why it held, what actually broke it, and whether the workarounds the industry has found deserve to carry the same name. The conversation moves from the elegant engine behind six decades of progress — shrinking transistors made chips simultaneously faster and cheaper, a combination almost unheard of in any other industry — to the quieter failure that came first. Dennard scaling, the physics reason that shrinking didn't cost more power, collapsed a full generation before quantum tunneling closed the door on further miniaturization below roughly three nanometers. The streak was already hollowing out before anyone hit the hard wall. From there, the episode gets into what 'progress' actually means now: process node names that no longer correspond to physical dimensions, lithography machines that cost over $350 million apiece, and a manufacturing frontier so expensive that it's economically justified only for AI accelerators. The alternatives — 3D stacking, chiplets, domain-specific architectures — are real and they work, but they trade one set of hard physics problems for another. Sixty years of exponential scaling taught every programmer alive to assume next year's chip would fix today's inefficiencies. What happens when that assumption stops being safe?

Frequently asked

Why does transistor scaling stop working below 3 nanometers?

Below roughly three nanometers, electrons behave as quantum waves rather than particles and tunnel through insulating barriers, creating uncontrollable leakage currents. This is a fundamental physics limit — not an engineering or funding problem — meaning no amount of investment can produce a conventional transistor workaround at those scales.

What is Dennard scaling and why did it break down?

Dennard scaling is the principle that shrinking a transistor by about 30 percent keeps power density constant, allowing higher clock speeds without extra heat. It broke down before physical transistor scaling did — chips kept getting denser, but the free energy efficiency gain disappeared, quietly raising power costs per generation before quantum limits became the headline problem.

Are '2nm' and '3nm' chips actually that small?

No. Process node names like '2nm' and '3nm' are technology-generation labels, not literal physical dimensions. Actual gate lengths and wire pitches no longer match the number on the label. The naming convention shifted as manufacturers needed a way to signal generational improvement after physical dimensions became too costly and complex to describe simply.

How much does it cost to manufacture chips at leading-edge nodes in 2025?

High-NA EUV lithography scanners — required to manufacture at leading-edge nodes — cost over $350 million per unit, and a fab needs multiple machines. Yield management grows harder and more expensive at every new generation. As a result, only TSMC, Samsung, and Intel can realistically manufacture at the frontier, and only for high-value workloads like AI accelerators.

What is replacing traditional transistor shrinking in chip design?

Chipmakers are shifting to 3D stacking, chiplets, and domain-specific accelerators. TSMC, Intel, and Samsung stack silicon dies vertically to increase density without shrinking transistors further. Apple's Neural Engine exemplifies architectural specialization — designing transistors for a specific workload rather than scaling raw transistor count. Each approach trades the old physics problem for new thermal and integration challenges.

Grounded in 12 sources
MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures ↗ · arxiv.org
Evaluation of Domain-Specific Architectures for General-Purpose Applications in Apple Silicon ↗ · arxiv.org
The Death of Moore’s Law: What it means and what might fill the gap going forward | CSAIL Alliances ↗ · cap.csail.mit.edu
3D ICs: The Near Future of Integrated Circuits ↗ · doi.org
A Review of Novel Chip Technologies amid the Slowdown of Moore's Law ↗ · doi.org
Smaller, Smarter, Speedier, Stacked: Engineering Next-Gen Computing ↗ · coe.gatech.edu
Moore’s Law and Its Practical Implications ↗ · csis.org
Moore's law | Computer Science | Research Starters | EBSCOhost ↗ · ebsco.com
Moore's law - Wikipedia ↗ · en.wikipedia.org
Die Shift in Chiplet Architectures: Challenges and Solutions ↗ · eureka.patsnap.com
Defining New Thresholds For Photolithography ... ↗ · eureka.patsnap.com
Challenges In Scaling Chips To 2nm And Below ↗ · semiengineering.com
Read transcript

Hope Sterling: Juniper, hey — okay I have to ask, did you do anything fun this week or did you just, like, read about transistors?

Juniper Vale: I mean, both, honestly. I was helping my nephew with a school project about inventions and I pulled up this fact and just — stopped. I couldn't move on.

Hope Sterling: Wait, what fact?

Juniper Vale: In 2012, researchers built a transistor out of a single atom. One atom. And that was five years ahead of where Moore's Law said we'd even need to be.

Hope Sterling: WAIT. One atom. And then what — we just stopped?

Juniper Vale: Basically. Chipmakers stopped chasing that direction entirely. And that's actually the part that I can't shake — we hit the target early, and then walked away from it.

Hope Sterling: This is what we're getting into today — Moore's Law, why it held for like sixty years, why it might be over, and whether that actually matters to the person buying the next iPhone. And I think the thing we're really trying to figure out is — was this inevitable? Like, was the wall always coming?

Juniper Vale: Right. And to even answer that, you have to back up to 1965. Gordon Moore — he was director of R&D at Fairchild Semiconductor at the time — published this article in Electronics magazine where he just... noticed a pattern. Integrated circuit component counts were doubling roughly every year.

Hope Sterling: He just noticed it. Like, he looked at the data and went — huh, that's a thing.

Juniper Vale: Exactly that. It wasn't derived from physics, it wasn't a theorem — it was an empirical observation. A recorded trend. The universe didn't promise anything.

Hope Sterling: Which is — okay, that's kind of wild, right? Because everyone treats it like gravity. Like it's a rule. And then Moore himself revised it in 1975 to doubling every two years, which is the version everyone quotes now, and still — still just an observation.

Juniper Vale: And yet it held, roughly, for sixty years. So the question sitting underneath all of this is — if nothing enforced it, why did it keep going?

Hope Sterling: Okay but that's the thing — WHY did it keep going? Like, nobody enforced it. There's no transistor police.

Juniper Vale: That's the part that gets me. It kept going because shrinking transistors did two things at once that almost never happen together — chips got faster AND cheaper. Same move, both benefits, automatically.

Hope Sterling: Wait — both at the same time? That's not how anything works.

Juniper Vale: Right? Normally you want the faster thing, you pay more. But with planar scaling — just fitting more transistors onto a flat silicon surface — you got the performance bump AND the price drop in the same generation. Think of it like... a family road trip where every year the car goes twice as far on the same tank of gas and also costs half as much. For sixty years running.

Hope Sterling: That's — I mean, that's insane. No other industry does that.

Juniper Vale: None. And that's what made it self-reinforcing — cheaper chips funded more R&D, which funded the next shrink, which made chips cheaper again. It was a loop. Gordon Moore noticed the loop; he didn't create it.

Hope Sterling: Wait, this is where Dennard comes in, right? Because I kept seeing his name and I need someone to just tell me what he actually said.

Juniper Vale: So Dennard scaling is basically the physics reason the loop worked. Every time you shrink a transistor by about thirty percent, the power density stays constant. So you can run faster — higher clock speeds — and not pay for it in extra heat or energy. That's the engine behind the road-trip analogy.

Hope Sterling: So it's like — the car getting faster without needing a bigger gas tank.

Juniper Vale: Exactly that. And — okay, this is the part I didn't see coming when I first read about it — Dennard scaling actually broke down before transistor density scaling did. The power advantage disappeared first. So the industry lost that free lunch on energy a full generation before the physical shrinking even hit its wall.

Hope Sterling: Wait — so the streak was already cracking from the inside? Like, quietly, before anyone hit the quantum tunneling problem?

Juniper Vale: From the inside. The car was still going farther, but it was quietly burning more gas each trip. And most people didn't notice because the mileage headline still looked good. That's the 'but' sitting underneath sixty years of exponential progress — it was already hollowing out before the physics finally said stop.

Hope Sterling: But — that's the thing, because the wall that finally said STOP? It's not a money problem or an engineering problem. Like, below roughly three nanometers, electrons just — they stop behaving like particles. They start behaving like waves. And waves don't respect walls.

Juniper Vale: Quantum tunneling.

Hope Sterling: QUANTUM TUNNELING. Which — okay, imagine a teenager throwing themselves at a wall over and over thinking if they just run faster they'll get through. More funding, same result. The wall does not care. That's what the insulating barrier is at sub-three nanometer scales — electrons are just passing through it, causing leakage currents, burning power in ways you can't predict or control.

Juniper Vale: And that distinction matters so much — because this isn't 'it's expensive right now.' It's not 'we need a breakthrough.' The universe literally does not offer a workaround here.

Hope Sterling: Right?! It's not a budget problem!

Juniper Vale: But — okay, wait, I want to push on this a little. Because IBM announced 2-nanometer chips in 2021. Which seems like, well, we went past three nanometers. So doesn't that break the story?

Hope Sterling: I had the same reaction and then I looked at it more and it's like, yes and also that's kind of the point? IBM demonstrated it. Which means the frontier moved. But the cost and difficulty of moving it that one tiny step — that's where the story actually is.

Juniper Vale: It's proof that you CAN push further. And also proof of exactly how punishing it is to do so. Both things are true at once.

Hope Sterling: Which — and this is where the naming thing breaks my brain a little — like, the chip IBM called '2 nanometer'? It is not actually two nanometers. That's a generation label. The actual transistor geometry is something completely different.

Juniper Vale: Yeah, process node names haven't been literal physical dimensions for a while now. '3 nm,' '2 nm' — those are technology-generation designators. The actual gate lengths, wire pitches, none of it matches the number on the label.

Hope Sterling: Is that just clever branding or is that actually deceiving people? Because those feel different to me and I genuinely don't know where the line is.

Juniper Vale: I don't know that I'd resolve it cleanly — and honestly the cost side of this makes it so much messier. Like, the reason the labels drifted from reality connects directly to what it now costs to manufacture at these nodes, which... we should get into that.

Hope Sterling: Wait — the cost is what made the labels drift? Like, those two things are actually connected?

Juniper Vale: They are. Because when you can't make chips literally smaller anymore without it costing an almost incomprehensible amount of money — the naming convention becomes a way to signal 'this generation is better' without having to explain what better actually means now.

Hope Sterling: Okay but HOW much money are we talking. Like, give me a number that hurts.

Juniper Vale: High-NA EUV lithography scanners — which you need to manufacture at the leading nodes right now — cost over three hundred and fifty million dollars. Per unit. Not per fab. Per machine.

Hope Sterling: Stop. Three hundred and fifty MILLION. For one machine.

Juniper Vale: One scanner. And you need multiple. And then yield management — actually getting usable chips off each wafer — gets harder and more expensive at every new generation. So the cost curve isn't linear, it's — I mean, it basically goes vertical at the frontier.

Hope Sterling: Which is why — okay, wait — is that why it's literally only TSMC, Samsung, and Intel who can even play at that level? Like, everybody else just... can't afford the ticket?

Juniper Vale: That's exactly it. And even they can only justify it for certain workloads — AI accelerators, high-performance computing. The broader world, most consumer chips, they're running on mature nodes. Twenty-eight nanometers and above. Which is — actually no, here's the part that reframes everything — twenty-eight nanometer is not bad. It's proven, it's cost-effective. But it's not what the marketing says is happening.

Hope Sterling: So when someone calls a chip '3 nm' — and it's not actually three nanometers — they're also hiding the fact that basically nobody outside of AI labs can afford what it takes to make that chip. It's like, the label does double work.

Juniper Vale: Double work, yeah. And Synopsys — their engineers describe how advanced packaging, through-silicon vias, backside power delivery — those are becoming the new frontier specifically because planar scaling is no longer cost-competitive for most applications. So even the cutting-edge move is now a workaround for the economics, not just the physics.

Hope Sterling: Okay this is the scenario that I keep getting stuck on — like, picture a semiconductor engineer at some mid-tier fabless company, they've designed a chip, the design is ready, and they sit down to look at the tape-out budget and realize — it's not that the chip can't go to TSMC's advanced node. It's that the per-wafer cost has moved so far that the economics only work if you're building an AI accelerator. Anything else and you're just lighting money on fire.

Juniper Vale: And that's the thing — that's not a failure of innovation. That engineer didn't do anything wrong. The cost cliff moved under them. Which is the part that doesn't show up when a company announces a new node name. The public hears 'progress.' The engineer's spreadsheet says something completely different.

Hope Sterling: And that's the thing that, like — okay, this is where I've landed and I don't totally love it — we're stacking instead of shrinking now. That's the move. TSMC, Intel, Samsung — they're all building chips vertically, layering silicon on silicon, because you can get more density without having to make the transistors themselves any smaller. Chiplets, 3D stacking, all of it. And part of me wants to call that ingenious and part of me is like... is this just a very expensive side door?

Juniper Vale: That's the question I can't resolve. Because stacking genuinely works — you get the density gains. But the heat. If you're compressing all that compute vertically, you're also stacking heat sources on top of each other, and dissipating that is a completely different engineering problem than the one we just escaped.

Hope Sterling: Trading one hard physics problem for another.

Juniper Vale: Potentially. And then there's the chiplet piece — breaking a monolithic chip into smaller specialized dies, connecting them through interposers or advanced packaging — that helps with yield, you can mix process nodes, it's genuinely flexible. But is that Moore's Law continuing? Or is it — I mean, it's a different mechanism. The transistor count on any single planar surface isn't doubling anymore.

Hope Sterling: Okay but what about — like, Apple's Neural Engine. That's a domain-specific accelerator, it's baked into Apple Silicon, it does AI tasks specifically and it does them fast without needing more transistors in the traditional sense. Doesn't that feel like a different answer entirely? Not stacking, not shrinking — just, build the chip for the exact job.

Juniper Vale: It is a different answer. And it works — for that job. GPUs, TPUs, NPUs — domain-specific accelerators all operate on the same idea: architectural specialization instead of raw density. You don't need more transistors if the ones you have are perfectly matched to the workload. But that only helps if you know the workload in advance.

Hope Sterling: Right — but the part that doesn't fit is, like, nobody has written the software playbook for a world where the hardware just... stops scaling predictably. Sixty years of exponential improvement and every programmer alive learned to code assuming next year's chip would bail them out of today's inefficiencies.

Juniper Vale: And if thermal limits in 3D stacking also plateau — which they might — that's genuinely new territory. Not 'hard.' New. Hardware roadmaps have been exponential since before most of us were born. Episodic progress is a different world.

Hope Sterling: I don't think I have a clean answer on whether this counts as Moore's Law or something else. And I think that's actually where I'm sitting. The mechanism shifted — away from planar scaling, permanently — and we're calling it by the same name because we need the story to keep going. Maybe that's fine. Maybe it's not. I genuinely don't know.

Juniper Vale: Yeah. Me neither. And I think that's the honest place we got to — which, honestly, feels right for a sixty-year streak finally running out of road. Thanks for thinking through it with me.

The physics wall: why transistor scaling hits diminishing returns below nanometer scales · Onpode