Juniper Vale: Finn, hey — quick question before we get into it: if I asked you right now what Moore's Law actually says, word for word, what would you tell me?
Finn Brooks: Oh man — okay, transistors double every two years? On a chip? Something like that?
Juniper Vale: That's the version everyone knows. But the original — Gordon Moore's actual 1965 Electronics Magazine article — said every year, not every two. And it wasn't about transistors in general. It was about the number of components on the cheapest integrated circuits doubling roughly every year. Cheapest. The whole thing was about cost.
Finn Brooks: Wait — cheapest? That's in there?
Juniper Vale: That's the part that gets dropped in every casual retelling. He was projecting a cost curve. Not a physics curve. The engine behind it was learning-by-doing — CMOS fabs got better with cumulative production volume, so manufacturing costs fell even as transistor counts climbed.
Finn Brooks: So it's more like — okay it's like a manufacturing experience curve, almost? The more you make the cheaper it gets, and that's what was doubling density.
Juniper Vale: Exactly. And then in 1975 Moore himself revised it — slowed it down from every year to every two years. So the canonical version, the one your textbook probably has, was already a correction. A slower forecast.
Finn Brooks: He revised it and we still built a religion around the revision. That's somehow worse?
Juniper Vale: I think that's why the 'end of Moore's Law' framing feels so dramatic and also so confused. People are mourning a physics law that was never a physics law. Feature sizes went from micrometers to single-digit nanometers over Moore's career — that happened — but it happened because factories got cheaper, not because nature required it.
Finn Brooks: And now we're asking whether the thing that's actually ending is the economics. Not the physics. Which — honestly, that reframes the whole conversation.
Juniper Vale: That's it. That's the whole thing we're trying to work out today.
Finn Brooks: Okay, because if it's economics — you can maybe engineer around it, right? But if it's physics, like actual quantum effects, that's a different kind of wall entirely.
Juniper Vale: That's exactly the turn — because the physics wall is not one thing. It's like, three things stacking on each other. And the first one is genuinely weird.
Finn Brooks: Okay wait, walk me through it — what's the actual mechanism? Like, photolithography, that's the word that keeps coming up — what is that actually doing?
Juniper Vale: You're essentially using light as a stencil. You shine progressively shorter wavelengths of light through a mask, it etches the transistor features onto silicon, and shorter wavelength means finer features. That's how you get from micrometers down to nanometers — you keep finding shorter light. The current frontier is extreme ultraviolet, EUV, and those machines are genuinely extraordinary pieces of engineering.
Finn Brooks: So it's literally — smaller ruler, finer lines, more transistors. Decades of that.
Juniper Vale: Decades of that. And then you hit sub-10 nanometers and something genuinely strange happens.
Finn Brooks: Okay this is the part — imagine a door with a lock. Classical physics says if the lock is engaged, you cannot walk through. You are stopped. But quantum mechanics says at small enough scales, the electron doesn't knock — it just... appears on the other side. That's quantum tunneling. The electron passes through the barrier that is supposed to stop it.
Juniper Vale: And that's not a metaphor, that's actually what's happening in the gate insulator. The electrons are leaking through — it's called leakage current — and it degrades whether the transistor is switching reliably and burns power constantly.
Finn Brooks: No factory trick fixes that. Right? Like — that's not a process problem.
Juniper Vale: That's the thing. It's a hard physical limit, not an engineering inconvenience. There's no planar CMOS design that sidesteps it. You can't fab your way out.
Finn Brooks: And then — wait, I mean it doesn't stop there — because independently, packing a hundred billion transistors into a fingernail-sized area, which IBM actually demonstrated with that prototype, means you're generating heat in an impossibly small space. It's cooking itself.
Juniper Vale: That's a completely separate wall. Power density. The heat per unit area just — at some threshold, you cannot remove it fast enough without either burning the device or spending prohibitive energy on cooling.
Finn Brooks: Two walls. Quantum tunneling and thermal runaway, and they're stacking. And then there's a third thing — short-channel effects? Surface scattering, gate losing control of the channel? It's like — the more you look the worse it gets.
Juniper Vale: Which is why IBM's prototype doubling density required stacking transistors in two vertical layers — that's the tell. When you can't shrink the features anymore, you start building up instead of in. The physics isn't bending. The architecture is.
Finn Brooks: Building up instead of in — okay, but that's not just a clever workaround, that's like a completely different industry, right? Because IBM stacking transistors in two vertical layers to hit a hundred billion on a fingernail-sized chip — that's not photolithography doing that. That's structural engineering doing that.
Juniper Vale: That's the tell. And it's why Intel and TSMC aren't quietly doing this on the side — it's their primary roadmap. Not a stopgap while they figure out smaller features. This is the plan.
Finn Brooks: Wait — primary? Not like, backup plan?
Juniper Vale: Primary. Heterogeneous integration, advanced packaging — those are the terms they're using in their actual roadmap language. Which means chiplets, 3D stacking, specialized dies assembled together. And the reason that matters is — I mean, the old model was one number. One metric. Transistors per area, cost per transistor, and everyone benefited from the same lithography shrink. The new model doesn't have that.
Finn Brooks: Walk me through — what is a chiplet actually doing that a normal chip isn't? Like physically, what's different?
Juniper Vale: You take what used to be one monolithic piece of silicon and you break it into tiles — chiplets — each manufactured separately, potentially on different process nodes, then assembled into a single package. So your memory controller doesn't have to be on the same node as your compute core. You mix and match.
Finn Brooks: Which actually — dude, that improves yield, because a smaller tile has fewer defects than one giant die that fails if any corner goes wrong.
Juniper Vale: Exactly. But it also means the design complexity just — it explodes. And that's where it gets real for someone actually building chips right now. Think about a startup founder designing an AI inference chip. Five years ago, she waits for the next TSMC node, costs drop, she's done. Now she's hiring a photolithography expert and a chiplet architecture specialist because those are two completely different bodies of knowledge.
Finn Brooks: She's not betting on one process shrink anymore. She's betting on her team.
Juniper Vale: On her team's ability to disaggregate the design across three different fabs and still hit margins. That's a fundamentally different risk profile.
Finn Brooks: And then on top of chiplets and 3D stacking you've got the specialized architecture stuff — AI accelerators optimized for matrix multiplication, neuromorphic chips doing spike-based computation — like, those aren't shrinking transistors at all. They're just asking a totally different question about where performance comes from.
Juniper Vale: ARM is probably the clearest example of the efficiency-first version of that shift. Low-power specialized designs — the performance gains come from architectural choices, not from brute-force scaling. You know, that was almost unthinkable as a primary strategy twenty years ago.
Finn Brooks: Because Moore's Law was so reliable you didn't have to be clever. You could just wait.
Juniper Vale: And now clever is the whole job. Which — okay, I want to flag something we haven't touched yet, because I think it's actually the deeper problem under all of this. The physics limits are real. But the thing that might matter more is that the economic contract Moore's Law quietly provided for sixty years — universal, predictable cost drops that every customer shared equally — that contract has no agreed successor. And the fragmentation of who can afford which specialized approach could end up being a harder wall than the lithography was.
Finn Brooks: Oh — wait, that's a different kind of crisis entirely.
Juniper Vale: That's the part we need to dig into next.
Finn Brooks: Okay but like — a different kind of crisis, that's underselling it. Because cost-per-transistor was the contract. That was the shared benchmark everyone pointed at. Chipmakers, customers, startups, everybody. And now that number doesn't even — wait, does it still exist as a metric? Like, can you actually calculate cost-per-transistor on a chiplet system?
Juniper Vale: That's actually the crux of it. You can't. Not cleanly. Because in a chiplet system you've got dies from different fabs, different nodes, different assembly costs — the integration complexity grows non-linearly in a way that CMOS fab never did. A straight CMOS shrink, learning-by-doing kicked in, you made more, it got cheaper, predictably. Chiplet assembly doesn't have that same curve.
Finn Brooks: Non-linearly — meaning it gets disproportionately harder as you add pieces?
Juniper Vale: Yeah. Each interface between chiplets is its own engineering problem. It doesn't just scale with the number of tiles.
Finn Brooks: So the IBM 0.7nm prototype — that's a lab demonstration. That's not a manufacturable node. Those are completely different things and we keep conflating them.
Juniper Vale: Completely different things. A research prototype shows physics can permit something. A manufacturable node means you can do it at volume, at yield, at a price someone actually pays. The economic constraint bites before the physics limit even gets tested.
Finn Brooks: Okay that is — I mean that's the thing nobody says out loud. The wall we're hitting might not be quantum tunneling. It might just be that nobody can afford to build the fab.
Juniper Vale: And that concentrates capability in a very small number of players. TSMC, Intel, maybe one or two others who can actually design and manufacture heterogeneous systems at scale. Which means — I don't know, that feels like it replaces the lithography bottleneck with a geopolitical and economic access bottleneck.
Finn Brooks: Wait — so specialization solves the power and performance problem for AI inference, right, but it actively fragments everything else. The general-purpose ecosystem. Like, who does this work for if you don't have a narrow workload to optimize for?
Juniper Vale: That's the fragmentation problem. And then there are the 2D materials on the research horizon — graphene, MoS₂, 2D tin monoxide — materials that keep their electrical properties at scales where silicon just degrades. But the gap between a lab transistor made of MoS₂ and a manufacturable process node is enormous. CMOS-compatible synthesis, large-scale uniform production — none of that is solved.
Finn Brooks: So post-silicon paths exist but none of them have cleared the cost hurdle. Not even close.
Juniper Vale: Not at scale. Which brings it back to the economic contract — Moore's Law gave everyone a shared, predictable benchmark for sixty years. What replaces it isn't one thing. It's whoever can afford the most specialized team, the most heterogeneous integration stack, access to the right fab partners. That's not a contract. That's a competition with very high entry costs.
Finn Brooks: And that competition is between — what, five companies globally? That's the next bottleneck. Not angstroms. Geopolitics.
Juniper Vale: Yeah, and — I mean, that's where I keep getting stuck. Not the angstroms. The access. Because the thing Moore's observation quietly did for sixty years was function as a shared floor. Everybody built on the same improving substrate. A startup in 1995, Intel, a university lab — the lithography shrink lifted all of them. That's gone. What replaces it is heterogeneous integration that costs more to design, requires more specialized knowledge, and concentrates at TSMC and maybe a handful of others. That's not a rising tide anymore.
Finn Brooks: And it started as an observation about the cheapest chips. He was literally watching costs fall and writing it down — not deriving it from first principles — and we turned it into sixty years of infrastructure assumptions.
Juniper Vale: He even walked it back himself in 1975. Slower doubling. And still we ran with it. I don't know — there's something almost clarifying about that. It didn't die from physics. It eroded from economics. That's a quieter ending than people expected.
Finn Brooks: Quieter and somehow heavier. Thanks for working through all of it — genuinely.
