Marcus Vale: Colette Kress said the words 'in fab' on an earnings call. That's it. Race over.
Ben Okonkwo: Hey — I literally just saw this before we recorded. Walk me through what 'in fab' actually means here, because I don't think people know what that transition is.
Marcus Vale: Tape-out. Nvidia handed finalized design data to TSMC. Physical wafers are in production right now. That is not a roadmap promise — that's irreversible. You can't un-tape-out a chip.
Ben Okonkwo: Right, and she named all of them — the Rubin GPU, the Vera CPU, CX9 Super NIC, NVLink 144 switch—
Marcus Vale: Spectrum X switch, silicon photonics processor. Seven chips. Not one GPU — a unified stack. And then CoreWeave actually brought up a Vera Rubin NVL72 rack on June 1st. Michael Dell confirmed it on LinkedIn. That's a supply-chain vote, not a press release.
Ben Okonkwo: So — what's the actual claim? AMD's already toast?
Ben Okonkwo: Hold on. Not toast — not yet. CoreWeave's June 1st rack is one rack. That's a single data point. The gap between first validation and broad enterprise deployment is — I mean, that's not a small gap historically.
Marcus Vale: Fair. What's the actual counter?
Ben Okonkwo: The benchmarks. Nvidia's claiming 5x inference performance, 10x lower cost-per-token versus Blackwell — but at what batch size? What precision? What model architecture? Nobody's specified. And AMD's 3.3x rack-level figure for Venice, the 256-core on TSMC 2nm — that's estimates, not direct benchmarks. These two numbers aren't even measuring the same thing. There's no neutral referee running an apples-to-apples workload.
Marcus Vale: So procurement teams are committing capital to unverified marketing claims.
Ben Okonkwo: Essentially, yeah. And AMD Helios is real — open-standard networking, HBM4 co-packaging, unveiled at CES 2026. Venice hitting 2nm production in May is actually a genuine technical milestone, first HPC product on that node. I'm not dismissing it. I just — actually, wait — the problem is AMD's marketing is overstating a figure nobody's validated against Vera Rubin directly.
Marcus Vale: Real question is — does that matter if hyperscalers already pre-committed before the tape runs?
Marcus Vale: The HBM4 story is where the hot take actually holds. All three — SK Hynix, Micron, Samsung — simultaneously hit volume shipping status for Vera Rubin by June. That's never happened before on any Nvidia GPU generation. Not once.
Ben Okonkwo: Wait — simultaneously? All three?
Marcus Vale: Micron announced high-volume production of 36 GB HBM4 at GTC March 2026. Hynix was first to volume. Samsung went from sampling to qualified. Same platform cycle. Nvidia deliberately engineered that — they gave up pricing leverage to kill the single-supplier chokepoint. That's a deliberate architecture decision worth fifty billion dollars buried in a supply chain footnote.
Ben Okonkwo: Right, and — okay, that actually does change the load-bearing assumption I was carrying. Because the single-vendor risk was my reason to doubt the June timeline. If that's removed from day one, the schedule becomes structurally credible in a way it wasn't before.
Marcus Vale: Now drop the France piece on top of that. Bull and Foxconn are manufacturing Vera Rubin NVL72 components at Bull's factory in Angers. France. AMD's Venice is entirely TSMC-dependent. Nvidia just quietly decoupled from single-geography fab risk at the platform level — 350-plus supply chain partners, European production live.
Ben Okonkwo: Angers, France. I — hm, that's the signal I genuinely missed. That's not cost management, that's geopolitical infrastructure positioning. And AMD's Helios open-networking pitch doesn't even reach the CUDA layer — it doesn't touch NIM. So whatever networking openness AMD is selling, the software moat is completely intact.
Marcus Vale: That's the partial win. Supply architecture — real moat. Benchmark claims — still unproven. But the structure underneath the claims? That's solid.
Ben Okonkwo: The part that strikes me — the timing is genuinely narrow. Venice production ramp started May 2026. Vera Rubin mass availability is late 2026. That's not a blowout gap. AMD is not dead in the water on the calendar. But here's what actually matters — if a hyperscaler trains their agentic models on Vera Rubin's NVLink fabric, switching to Helios is not a hardware swap. That's a full rewrite. The lock-in question gets answered by procurement decisions made right now, on numbers nobody's independently verified.
Marcus Vale: Fine. Benchmarks unverified. I'll spot you that. Name me one hyperscaler rewriting their CUDA stack on a Venice benchmark claim.
Ben Okonkwo: That's exactly it. By the time Venice ships in volume, the lock-in question is already closed — decided on unverified numbers, before any neutral workload ever ran.
