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Cover art for The memory wall: why bandwidth matters more than raw compute for AI workloads

The memory wall: why bandwidth matters more than raw compute for AI workloads

July 30, 2026 · 8 min

Iris Holm & Hana Field

For AI inference workloads, memory bandwidth — not peak FLOPS — sets the speed limit. Every generated token requires pulling the full model weight set through memory. Token generation speed equals roughly memory bandwidth divided by bytes-per-token. Doubling a GPU's FLOPS while holding bandwidth constant produces nearly identical inference latency, often at higher power cost.

AI inference and training performance is primarily constrained by memory bandwidth — the rate at which data moves between high-bandwidth memory (HBM) and compute cores — rather than by peak floating-point throughput (TFLOPS).

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About this episode

Everyone in AI talks about compute. FLOPS are on every spec sheet, every press release, every procurement bid. But for the workload that actually runs at scale — inference, generating tokens in response to user queries — compute stopped being the constraint a long time ago. Memory bandwidth is the ceiling, and it has been for decades. This episode works through why. The core issue is something called arithmetic intensity: the ratio of math operations to bytes moved. Inference has very low arithmetic intensity. You do a small amount of computation per byte transferred. That puts it squarely in memory-bound territory on the roofline model — a framework from 2009 that the industry has underused ever since. The implications are uncomfortable. A chip with twice the FLOPS and the same memory bandwidth runs inference at nearly identical speed — while drawing more power. The spec sheet is answering a different question than the one your latency numbers will ask. The episode also traces what the hardware response looks like: Nvidia's Blackwell B200 pushing memory bandwidth to 8 TB/s with HBM3E stacking, at a cost of 1,000 watts per GPU and a liquid-cooling requirement most data centers weren't built for. And then the software response — quantization — which works mathematically but quietly narrows the precision of every model it touches, usually without the people depending on those outputs knowing it happened. The memory wall is a technical problem. But by the end, it starts to look like something else too.

Frequently asked

Why does memory bandwidth matter more than FLOPS for AI inference?

AI inference is memory-bound because autoregressive token generation must reload the full model weight set from VRAM on every single decoding step. Token generation speed equals approximately memory bandwidth divided by bytes-per-token — not a function of peak TFLOPS. The roofline model, developed by Williams, Waterman, and Patterson in 2009, confirms LLM inference decoding sits well below the compute-bound threshold.

What is arithmetic intensity and how does it apply to LLM inference?

Arithmetic intensity is the ratio of floating-point operations to bytes of memory moved, measured in FLOPs per byte. The 2009 roofline model uses this ratio to determine whether a workload is memory-bound or compute-bound. LLM inference decoding has very low arithmetic intensity — very little math per byte moved — placing it firmly in memory-bound territory, not borderline.

How much memory bandwidth does the Nvidia B200 GPU have compared to the H100?

The Nvidia B200 delivers approximately 8 terabytes per second of memory bandwidth via HBM3E stacking, compared to 3.35 TB/s on the H100 and 4.8 TB/s on the H200. That bandwidth increase comes at a cost: the B200's thermal design power reaches 1,000 watts, up from 700W on the H100 and H200, requiring liquid cooling infrastructure most data centers lack.

Does quantization (FP8, FP4) help with the AI memory wall?

Quantization reduces the bytes-per-token cost of inference, which effectively increases available memory bandwidth per token and shifts the workload up the arithmetic-intensity axis toward compute-bound territory. FP8 or FP4 precision can approximately halve the bytes moved per step. However, quantization trades numerical precision for throughput — a tradeoff made by whoever configures the deployment stack, often invisible to downstream users.

Why do GPU spec sheets mislead AI infrastructure buyers about inference performance?

GPU spec sheets lead with peak FLOPS — the H100 lists 141 petaFLOPS — but inference latency is determined by memory bandwidth, not compute throughput. A GPU with twice the FLOPS and identical memory bandwidth produces nearly the same inference speed while consuming more power, worsening cost-per-token. The binding constraint for inference workloads does not appear on standard specification sheets.

Grounded in 7 sources
AI and Memory Wall · arxiv.org
Microbenchmarking NVIDIA’s Blackwell Architecture: An in-depth Architectural Analysis · arxiv.org
Performance Modeling and Workload Analysis of Distributed Large Language Model Training and Inference · arxiv.org
GPU Server Buyer's Guide: H100 vs H200 vs B200 | Jon Moen | Adam Silva Consulting · adamsilvaconsulting.com
So You Need Enterprise GPUs - A No-BS Guide to H100, H200, and B200 - Open Infrastructure Blog · blog.rackspacecloud.com
Hardware & Memory: Why Bandwidth Beats FLOPS — Inference Engineering · inference-engineering.com
Token throughput and the memory wall: why decode is bandwidth-bound – ITK Research · itkservices3.com
Read transcript

Iris Holm: Quick question before we start — did you look at the Gholami paper?

Hana Field: I did, yeah — and honestly the chart on page one stopped me cold. What was your reaction to it?

Iris Holm: 3.0 times versus 1.6 times. Compute versus memory bandwidth. Two decades. It's not a performance gap — it's a measurement gap. The whole industry has been pointing at the wrong ceiling.

Hana Field: And the thing is, you'd never know it from how these chips get sold — like, the H100 spec sheet leads with 141 petaFLOPS, and that number is just enormous and impressive, and it's also, according to the UC Berkeley team, largely beside the point for inference workloads.

Iris Holm: Right — a GPU with twice the FLOPS and the same memory bandwidth will run inference at nearly the same speed. That's not a footnote. That's the finding.

Hana Field: Hmm, which makes me wonder what the procurement officer story actually feels like from the inside — someone reads that spec sheet in good faith, they deploy on Nvidia's hardware, and then the inference latency barely moves.

Iris Holm: Frankly, that's the failure mode nobody wants to name. So today we're getting into why compute scaling stopped being the constraint — and what actually is.

Hana Field: And if compute has raced ahead for twenty years, why does the data say it barely matters for inference — that's the thing I want to actually understand by the end of this.

Iris Holm: Think of it like a kitchen. Big commercial kitchen — full of chefs, every burner going, all of them standing there ready. Now there's one door. One delivery door. Every ingredient comes through that one door. The chefs can cook as fast as you like. They cannot cook faster than ingredients arrive.

Hana Field: And the door is memory bandwidth.

Iris Holm: That's the whole thing. Token generation speed is approximately memory bandwidth divided by bytes-per-token. Not a function of peak TFLOPS. That's the sentence.

Hana Field: Wait — so every single token we generate, the whole model has to come through that door? Like, every time?

Iris Holm: Every token. Full weight set. Every time. The model doesn't stay loaded — it gets pulled from VRAM back through that pipe on each generation step. So you've got this enormous compute engine sitting there and it's waiting. Every. Single. Token.

Hana Field: That's — okay, that reframes the entire procurement story we were just telling. Because the chefs aren't the problem. Adding more chefs does nothing if the door doesn't get wider.

Iris Holm: Right. And here's where the arithmetic intensity framing — Williams, Waterman, Patterson, the 2009 roofline model — becomes the actual diagnostic. It's not headline TFLOPS. It's FLOPs per byte. That ratio is what tells you whether you're memory-bound or compute-bound. Inference has very low arithmetic intensity. You do a small amount of math per byte moved. So the roofline says: memory-bound, full stop.

Hana Field: So the spec sheet number — the petaFLOPS — it's measuring the chefs. And nobody's measuring the door.

Iris Holm: Exactly — and the ridge point is where that distinction gets precise. Williams, Waterman, and Patterson's 2009 framework draws a line: below a certain arithmetic intensity, you are memory-bound; above it, compute-bound. That line is the ridge point. LLM inference decoding lives well below it. Not close. Not borderline.

Hana Field: Wait — so there's an actual threshold? Like a specific number you cross?

Iris Holm: The ridge point shifts by hardware, but the ratio is the same diagnostic. FLOPs per byte. If your kernel does very little math per byte it moves, you land left of the ridge. Memory-bound. And autoregressive decoding — one token at a time, pulling the full weight set each step — that's one of the lowest-intensity operations you can run on a GPU.

Hana Field: So picture that infrastructure lead — Sunday afternoon, she's comparing procurement bids, H100 spec sheets across three vendors — and every number in front of her is a TFLOPS figure. 141 petaFLOPS here, something slightly higher there. And the roofline model is saying... none of that matters for what she's actually buying the chip to do.

Iris Holm: None of it. The ceiling that binds her workload isn't on that sheet.

Hana Field: She's not making a bad decision, you know? She's reading the document she was given. It's just that the document is answering a different question than the one her latency numbers will ask.

Iris Holm: Right, but — actually, that's where I'd push slightly. A GPU with twice the TFLOPS and the same memory bandwidth doesn't just run inference at the same speed. It can run it at nearly identical speed *while consuming more power*. So it's not neutral. It's actively worse on cost-per-token.

Hana Field: Oh — that's a sharper version of the problem than I had.

Iris Holm: And it gets sharper. Because the answer — the actual architectural response to the memory wall — is what Nvidia's Blackwell B200 attempts with HBM3E stacking and the NVLink scaling. Eight terabytes per second. That part we need to get to, because the solution generates its own set of constraints that are — frankly — not on any spec sheet either.

Hana Field: Eight terabytes per second, though — I mean, going from the H100's 3.35 to the H200's 4.8 and then jumping all the way to 8.0 on the B200, that's not incremental. That's a different kind of architectural bet, and I keep wondering what it actually costs to cash it in.

Iris Holm: It costs a thousand watts.

Hana Field: Wait — per GPU?

Iris Holm: B200 TDP hits 1000W. H100 and H200 both sat at 700W. That 300-watt jump isn't incidental — HBM3E stacking physically moves DRAM dies closer to the compute die, you're pushing data faster, and that demands more energy. The power envelope is what the bandwidth costs. And 1000W means liquid cooling, which most data centers don't have.

Hana Field: So the solution to the memory wall requires infrastructure that — and this is the part that gets me — wasn't part of the problem. You solved one thing and generated a prerequisite that didn't exist before.

Iris Holm: Right — and it compounds. NVLink scaling from 900 GB/s on the H100 to 1.8 TB/s on the B200, that sounds like the second win. But wait, actually — that's solving a second-order problem. You needed faster inter-GPU links because per-GPU bandwidth was the first bottleneck. NVLink at 1.8 terabytes is the solution to a problem the original problem created.

Hana Field: That's — huh. So it's not a feature. It's a consequence.

Iris Holm: And then there's the 192 gigabytes of HBM capacity on the B200 — which helps because you reload weights less often across inference steps — but HBM supply is constrained. So: one scarcity solved, three others created. Power. Cooling infrastructure. Memory supply. None of that is on the spec sheet.

Hana Field: And so that data center ops person — they're not making a bad call by wanting the B200. They're just inheriting a different set of walls than the ones Nvidia announced they'd taken down.

Iris Holm: There is a software-side answer, though. FP8, FP4 quantization — you halve the bytes-per-token, you've just effectively doubled your bandwidth. The roofline shifts. You move up the arithmetic-intensity axis toward compute-bound territory. Mathematically, it works.

Hana Field: Right — but the roofline tells you *that* the trade happened, not whether it was okay to make it. And I keep sitting with this: somewhere between Gholami's paper and a deployed model running FP4, someone decided how much precision was acceptable to sacrifice for throughput. And I'm not sure the people depending on that model's output were ever in that room.

Iris Holm: That's — yeah. The math doesn't resolve that. The math just says the tradeoff is available.

Hana Field: And training's a bit different — higher arithmetic intensity, closer to compute-bound, so the memory wall bites less hard there. But for inference at scale, the quantization decision is being made by whoever configures the deployment stack, and it's... I don't know, it's kind of invisible to everyone downstream.

Iris Holm: We started with a chart — 3.0 times versus 1.6 times, two decades, nobody measuring the door. And we end with: someone quietly narrowed what fits through the door, and called it a solution.

Hana Field: The door got wider and smaller at the same time, depending on who you ask. I'll be thinking about that one for a while. Thank you for working through it with me.